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general description the ds1881 is a dual, nonvolatile (nv) digital poten-tiometer designed to operate in audio systems that require 5v signal levels. the potentiometer settings can be stored in eeprom so that they are retained when the power is cycled. the ds1881 has separate supplies for the potentiometers (v cc ) and the communication circuit- ry (v dd ). for clickless/popless operation, a zero-crossing detector allows the wiper position to change when thereis no voltage across the potentiometer. the device is also designed to minimize crosstalk, and the two digital potentiometers provide 0.5db channel-to-channel match- ing to prevent volume differences between channels. total harmonic distortion (thd) is also minimal as long as the wiper drives a high-impedance load. two attenuation configuration options provide optimum flexibility for the specific application. configuration option 1 provides 63 logarithmic tapered steps (0db to -62db, 1db/step) plus a mute setting. configuration option 2 has 32 logarithmic steps plus mute and pro- vides software compatibility with the ds1808. when configuration option 2 is used in combination with the 16-pin so package, the ds1881 is both software and pin compatible with the ds1808 in 5v applications. applications notebook and pc audioportable audio equipment car stereo consumer audio/video features ? dual, audio log taper potentiometers ? low thd+n and crosstalk ? 5v analog supply (independent of digital supply) ? 3v to 5v digital supply range ? potentiometer settings configurable as nv or volatile ? zero-crossing detector eliminates switchingnoise ? two user-configurable attenuation options ? configuration option 1: 63 positions provide 1dbattenuation steps from 0db to -62db plus mute ? configuration option 2: (software-compatiblewith the ds1808): 33 positions plus mute as follows positions 0?2: 1db per step for 12 stepspositions 13?4: 2db per step for 12 steps positions 25?2: 3db per step for 8 steps ? i 2 c-compatible serial interface ? three address pins allow up to 8 devices on i 2 c bus ? 45k potentiometer end-to-end resistance ? industrial temperature range (-40? to +85?) ? 16-pin tssop or so package ds1881 dual nv audio taper digital potentiometer ______________________________________________ maxim integrated products 1 1615 14 13 12 11 10 1 23 45 6 7 v dd v cc sclsda n.c. a1 a2 gnd top view ce w1 h1 l0 w0 9 8l 1 h0 a0 tssop/so ds1881 + pin configuration rev 0; 1/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes lead-free package. ordering information part temp range version (k ) pin-package ds1881e-050+ -40? to +85 c 45 16 tssop(173 mils) ds1881e-050+t&r -40? to +85 c 45 16 ts s o p ( 173 m i l s) tap e- and - reel ds1881z-050+ -40? to +85 c 45 16 s o ( 150 m i l s) ds1881z-050+t&r -40? to +85 c 45 16 s o ( 150 m i l s) tap e- and - reel typical operating circuit appears at end of data sheet. downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions(t a = -40? to +85?) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v dd , sda, and scl relative to gnd .....-0.5v to +6.0v voltage on a2, a1, a0, and ce relative to gnd .................-0.5v to (v dd + 0.5v), not to exceed +6.0v voltage on v cc relative to gnd ...........................-0.5v to +6.0v voltage on h1, h0, w1, w0, l1, and l0 relative to gnd...............................................................-0.5v to +6.0v maximum resistor current .................................................?ma operating temperature range ...........................-40? to +85? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units digital supply voltage v dd (notes 1, 2) 2.7 5.5 v analog supply range v cc (notes 1, 2) 4.5 5.5 v potentiometer voltages 0 5.5 v wiper current ? ma dc electrical characteristics(v dd = +2.7v to +5.5v, v cc = +4.5v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units digital supply current i dd (note 3) 200 250 ? analog supply current i cc (note 4) 0.9 5 a input logic 0( ce , sda, scl, a0, a1, a2) v il (note 5) -0.3 0.3x v dd v input logic 1( ce , sda, scl, a0, a1, a2) v ih (note 5) 0.7 x v dd v dd + 0.3 v i ol = 4ma 0.4 output-voltage low (sda) v ol i ol = 6ma 0.6 v input leakage current i li -1 +1 ? i/o pin input current (sda) 0.4v < v sda < (0.9 x v cc ) -10 +10 ? i/o capacitance c i/o (note 6) 10 pf power-up time t pu 1m s downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer _____________________________________________________________________ 3 i 2 c characteristics (see figure 4) (v dd = +2.7v to +5.5v, v cc = +4.5v to +5.5v, t a = -40 c to +85 c. timing referenced to v il(max) and v ih(min) .) parameter symbol conditions min typ max units scl clock frequency f scl (note 9) 0 400 khz bus free time between stop andstart conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 10) 20 + 0.1c b 300 ns sda and scl fall time t f (note 10) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 10) 400 pf eeprom write time t w (note 11) 5 10 ms analog potentiometer characteristics(v dd = +2.7v to +5.5v, v cc = +4.5v to +5.5v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units end-to-end resistance r ee +25 c4 5 k end-to-end resistance tolerance +25 c -20 +20 % ratiometric temperature coefficient (note 6) 30 ppm/ c end-to-end resistance temperaturecoefficient (note 6) 750 ppm/ c wiper resistance r w 160 250 absolute attenuation tolerance (note 7) -0.5 +0.5 db mute position attenuation 80 db step size deviation from nominal (note 7) -0.25 +0.25 db interchannel matching (note 7) -0.5 +0.5 db -3db cutoff frequency 10pf load 5 mhz output noise (20hz to 20khz, grounded input,tap = -6db) 2.2 ? rms crosstalk (1khz, grounded input, tap = -6db) -110 db thd+n 1khz, tap = -6db, c l = 10pf (note 8) 0.005 % zero-crossing detection t zcd 38 50 ms downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 4 _____________________________________________________________________ nv memory characteristics(v dd = +2.7v to +5.5v, v cc = +4.5v to +5.5v, t a = 0 c to +70 c.) parameter symbol conditions min typ max units writes +70 c (note 6) 50,000 note 1: all voltages are referenced to ground. note 2: the value of v dd should never exceed v cc , including during power-ups. v cc must be applied before v dd . note 3: i dd is specified with sda = scl = ce = v dd , resistor pins floating, and digital inputs connected to v dd or gnd. note 4: i cc is specified with sda = scl = ce = v dd , resistor pins floating, and digital inputs connected to v dd or gnd, after zero- crossing detection has timed out. note 5: the ds1881 will not obstruct the sda and scl lines if v dd is switched off as long as the voltages applied to these inputs do not violate their minimum and maximum input voltage levels. note 6: guaranteed by design. note 7: above position 50, these are typical maximum. guaranteed by characterization. note 8: load is representative of the input of a low-noise audio amp. note 9: timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard-mode timing. note 10: c b total capacitance of one bus line in picofarads. note 11: if zero-crossing detection is enabled, the eeprom write does not begin until the current zero-crossing detection is com- plete. otherwise, eeprom write begins after a stop condition occurs. i dd vs. v dd ds1881 toc01 voltage (v) supply current ( a) 5.3 5.1 4.7 4.9 120 140 160 180 200 220 240 260 280 300100 4.5 5.5 sda = scl = v cc i dd vs. temperature ds1881 toc02 temperature ( c) supply current ( a) 80 60 -20 0 20 40 50 100 150 200 250 300 350 400 0 -40 sda = scl = v dd i dd vs. scl frequency ds1881 toc03 scl frequency (khz) active supply current ( a) 400 300 350 250 50 100 150 200 50 100 150 200 250 300 350 400 0 0 sda = v dd typical operating characteristics (v dd = v cc = +5.0v, t a = +25 c.) downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer _____________________________________________________________________ 5 potentiometer 0 (configuraton 1) attenuation vs. setting ds1881 toc04 setting (dec) attenuation (db) 54 45 36 27 18 9 -80.0 -60.0 -40.0 -20.0 0 -100.0 06 3 potentiometer 0 (configuraton 2) attenuation vs. setting ds1881 toc05 setting (dec) attenuation (db) 30 24 18 12 6 -80.0 -60.0 -40.0 -20.0 0 -100.0 03 3 27 21 15 9 3 potentiometer 1 (configuraton 1) attenuation vs. setting ds1881 toc06 setting (dec) attenuation (db) 54 36 18 -80.0 -60.0 -40.0 -20.0 0 -100.0 06 3 45 27 9 potentiometer 1 (configuraton 2) attenuation vs. setting ds1881 toc07 setting (dec) attenuation (db) 30 24 18 12 6 -80.0 -60.0 -40.0 -20.0 0 -100.0 03 3 27 21 15 9 3 end-to-end resistance percent change from +25 c vs. temperature ds1881 toc08 temperature ( c) resistance % change (from +25 c) 40 20 0 -20 -2.0 -1.5 -0.5-1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -2.5 -40 80 60 potentiometer 1 potentiometer 0 resistance vs. power-down voltage ds1881 toc10 power-up voltage (v) resistance (k ) 5 4 3 2 1 20 40 60 80 100 0 0 programmedresistance (-6db) mute supply current vs. zero-crossing timing ds1881 toc11 time (ms) i cc ( a) 100 200 300 400 500 600 700 800 900 1000 0 zero-crossingtimeout or zero- crossing event zero-crossingdetection activated typicaltimeout of 50ms typical operating characteristics (continued) (v dd = v cc = +5.0v, t a = +25 c.) resistance vs. power-up voltage ds1881 toc09 power-up voltage (v) resistance (k ) 5 4 3 2 1 20 40 60 80 100 0 0 high impedance programmedresistance (-6db) mute whileeeprom loads downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 6 _____________________________________________________________________ pin description pin name function 1 gnd ground 2a 2 3a 1 i 2 c address inputs. inputs a0, a1, and a2 determine the i 2 c slave address of the device. 4 n.c. no connection 5a 0 i 2 c address input. inputs a0, a1, and a2 determine the i 2 c slave address of the device. 6 w0 wiper terminal for potentiometer 0 7 l0 low terminal for potentiometer 0 8 h0 high terminal for potentiometer 0 9 l1 low terminal for potentiometer 1 10 h1 high terminal for potentiometer 1 11 w1 wiper terminal for potentiometer 1 12 ce chip enable. enables sda and scl pins for i 2 c communication. 13 sda i 2 c serial-data open-drain i/o 14 scl i 2 c serial-clock input 15 v cc analog voltage supply 16 v dd digital voltage supply thd+n vs. frequency (0db) ds1881 toc12 frequency (khz) thd+n (%) 10 1 0.1 0.0002 0.0004 0.0006 0.0008 0.0010 0.0012 0.0014 0.0016 0.0018 0 0.01 100 crosstalk vs. frequency (-6db) ds1881 toc13 frequency (khz) crosstalk (db) 10 1 0.1 -120 -100 -80 -60 -40 -20 0 -140 0.01 100 typical operating characteristics (continued) (v dd = v cc = +5.0v, t a = +25 c.) downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer _____________________________________________________________________ 7 decoder potentiometer 0 value configuration register potentiometer setting registers gnd zero-crossing detector h0 w0 l0 update update h1w1 l1 i 2 c interface sda scl a2a0 a1 ce v cc v cc v dd v dd gnd zero-crossing detector potentiometer 1 value ds1881 block diagram downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 8 _____________________________________________________________________ detailed description the ds1881 is a dual-channel, digitally controlled,audio potentiometer. the block diagram illustrates the features of the ds1881. the following sections discussthese features in detail. potentiometer configurations the ds1881 potentiometers have two possible attenua-tion configuration options. the configuration register section discusses how to change between the twooptions. note that both potentiometers are always set to the same option. the factory default for both potentiometers is option 1 (see table 1). option 1 provides 64 positions with 1db attenuation per step for positions 0 through 62 and mute as position 63. option 2 (see table 2) is a 34- position configuration. from position 0, the first 12 steps have 1db attenuation per step, the next 12 have 2db attenuation per step, and the following 8 steps have 3db attenuation per step. the last position, posi- tion 33, is the mute setting. zero-crossing detection zero-crossing detection is a user-selectable featureused to help eliminate clicking or popping noises dur- ing changes of potentiometer settings. see the configuration register section to learn how to enable the zero-crossing detection feature.after the i 2 c master issues a command to change the wiper position and the ds1881 has responded with anacknowledge (ack) to the command, the ds1881 has a 50ms window to change the wiper position. the ds1881 constantly monitors the voltage of the high and low terminals of both potentiometers. during the 50ms window, if the zero-crossing detection is enabled, then each potentiometer s wiper will change position if the high and low terminals of the same potentiometerbecome equal in potential (i.e., the magnitude of the input signal is zero). if a zero-crossing event does not occur within the 50ms window, then the wiper is allowed to change to the new position regardless of the state of the input signal. when the zero-crossing detec- tion feature is not enabled, the ds1881 will allow wiper movement as soon as the ds1881 has issued the acknowledge to the master-controlling device. table 1. configuration option 1 tap position attenuation (db) 00 11 22 33 44 55 66 77 88 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62 62 63 80 downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer _____________________________________________________________________ 9 command byte the command byte determines both the potentiometer wiper settings and the configuration of both poten- tiometers. this is done by setting the two msbs of the command byte to one of three values. if 00 is set as the value for the two msbs, then the wiper setting for potentiometer 0 is to be programmed. if 01 is set as the value, then the wiper setting of potentiometer 1 is to be programmed. see the potentiometer wiper setting sec- tion for more details about writing the wiper setting. avalue of 10 indicates that the configuration register is to be programmed. a value of 11 is reserved and is not to be used. see the configuration register section for more information. any values other than the three dis-cussed above will result in no action by the part. see below for the command byte structure. table 2. configuration option 2 tap position attenuation (db) 00 11 22 33 44 55 66 77 88 99 10 10 11 11 12 12 13 14 14 16 15 18 16 20 17 22 18 24 19 26 20 28 21 30 22 32 23 34 24 36 25 39 26 42 27 45 28 48 29 51 30 54 31 57 32 60 33 80 msb configuration selection register settings lsb command byte structure downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 10 ____________________________________________________________________ potentiometer wiper setting if 00 or 01 are the values of the two msbs of the command byte, then the wiper settings of the poten- tiometers are to be programmed. the lower 6 lsbs of the command byte are then used to store the wipersettings for the selected potentiometer. see below for the potentiometer wiper setting details. potentiometer wiper register factory default: xx111111b memory type: nv (eeprom) 0 x wiper setting b7 b6 b5 b4 b3 b2 b1 b0 bits 7, 6 configuration selection: selects which potentiometer will be programmed. 00 = potentiometer 0 will be programmed.01 = potentiometer 1 will be programmed. bits 5 0 these bits determine the wiper setting of the selected potentiometer. available wiper settings are determined bythe attenuation option as described in the configuration register section. downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer ____________________________________________________________________ 11 configuration register if 10 is entered as the value of the two msbs of thecommand byte, then the configuration register is to be modified. the three lsbs of the configuration register control the nv/volatile wiper setting, the zero-crossing detection feature, and the potentiometer atten- uation configuration. configuration register factory default: 87h memory type: nv (eeprom) 1 0 x x x v/nv control zero- crossing pot config b7 b6 b5 b4 b3 b2 b1 b0 bits 7, 6 configuration selection: when bit 7 is set to a 1 and bit 6 is set to a 0, the following configuration bits can be set and stored in eeprom. bits 5, 4, 3 these bits have no function. bit 2 volatile/nonvolatile potentiometer register control bit: a control bit that sets the potentiometer registers to be either volatile or nonvolatile memory.0 = potentiometer registers are set to nonvolatile memory storage. 1 = potentiometer registers are set to volatile memory storage. on power-up, the potentiometer wipers are in the mute position (default). bit 1 zero-crossing detection enable bit: a bit used to enable and disable the zero-crossing functionality. 0 = zero-crossing detection is disabled.1 = zero-crossing detection is enabled (default). bit 0 potentiometer position configuration: a control bit used to select the number of positions both potentiometers have.0 = potentiometers have 63 positions and mute. 1 = potentiometers have 33 positions and mute (default). downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 12 ____________________________________________________________________ i 2 c interface for the ds1881 the ce pin serves as a communication enable pin. when active ( ce = 0), the inputs sda and scl are rec- ognized by the device. if inactive ( ce = 1), pins sda and scl are disabled, making i 2 c communication impossible.three pins, a0, a1, a2, serve as slave address inputs. for multidrop configurations, they allow eight such devices to be addressed by the same i 2 c bus. if the i 2 c address matches the hardware levels of these bits, the ds1881 is allowed to receive communications fromthe i 2 c bus. the i 2 c slave address byte is shown below. this is the first byte transmitted from the master to the ds1881.the upper nibble value is fixed to 0101. bit values a2, a1, and a0 are determined by the states of the corre- sponding pins. the lsb, r/ w , determines whether a read or write will be performed.the next byte to be transmitted is the command byte (see the command byte section for details). read protocol 00 msb lsb pot-0 10 msb lsb pot-1 a0 a1 a2 1 101 0 msb lsb r/w = 1 data bytes are read in the order shown above. command byte command byte command byte slave address byte msb lsb config reg 10 start ackack ack ack stop figure 1. read protocol slave address byte 0 1 0 1 a 2a 1a 0r / w msb lsb reading pot values as shown in figure 1, the ds1881 provides one read command operation. this operation allows the user to read both potentiometer wiper setting registers and the configuration register. to initiate a read operation, the r/ w bit of the slave address byte is set to 1. communication to read the ds1881 begins with astart condition, which is issued by the master device. the slave address byte sent from the master device fol- lows the start condition. once a matching slave address byte has been received by the ds1881, the ds1881 responds with an acknowledge. the master can then begin to receive data. the value of the wiper of potentiometer 0 is the first returned from the ds1881.it is then followed by the value of potentiometer 1 and then the value of the configuration register. once the 8 bits of the configuration register have been sent, the master needs to issue an acknowledge, unless it is the last byte to be read, in which case the master issues a not acknowledge. if desired, the master may stop the communication transfer at this point by issuing the stop condition after the not acknowledge. however, if the value of the three registers is needed again, the transfer can continue by clocking the 8 bits of the potentiometer 0 value as described above. downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer ____________________________________________________________________ 13 writing command byte values an example of writing to the ds1881 is shown in figure 2. the ds1881 has one write command that is used to change the potentiometer wiper setting registers and the configuration register. all write operations begin with a start from the master, followed by a slave addressbyte. the r/ w bit should be written to 0, which initiates a write command. once the slave address byte hasbeen issued and the master receives the acknowledge from the ds1881, potentiometer wiper data is transmit- ted to the ds1881 by the master device. if the potentiometer has been configured to be written in nonvolatile memory (see the configuration register section), then the acknowledge needs to be followedwith a stop command. this command is required from the master at the end of data transmission to initiate the eeprom write. the stop command is also accepted if the user has configured the pot values to be written in volatile memory, but no eeprom is written to. i 2 c serial interface descriptions i 2 c interface supports a bidirectional data transmission protocol with device addressing. a device that sendsdata on the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1881 operates as a slave on the i 2 c bus. connections to the bus are made by the open-drain i/o lines, sda and scl. the following i/o terminals control the i 2 c serial port: ce , sda, scl, a0, a1, and a2. a data transfer protocol and a timing diagram are provided infigures 3 and 4. the following terminology is commonly used to describe i 2 c data transfers. i 2 c definitions master device: the master device controls the slave devices on the bus. the master device generates sclclock pulses, start and stop conditions. slave devices: slave devices send and receive data at the master s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and intheir logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave.transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave.transitioning sda from low to high while scl remains high generates a stop condition. see the timing dia- gram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans-fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid andunchanged during the entire high pulse of scl plus the setup and hold-time requirements (see figure 4). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of write protocol 00 msb lsb pot-0 10 msb lsb pot-1 a0 a1 a2 0 101 0 msb lsb r/w = 0 data bytes can be written in any order. command byte command byte command byte slave address byte msb lsb config reg 10 start ackack ack ack stop figure 2. write protocol downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer 14 ____________________________________________________________________ setup time (see figure 4) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slaveduring a write operation) performs an ack by transmit- ting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing (figure 4) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3C7 figure 3. data transfer protocol sdascl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf note: timing is referenced to v il(max) and v ih(min) . figure 4. i 2 c timing diagram downloaded from: http:///
ds1881 dual nv audio taper digital potentiometer ____________________________________________________________________ 15 byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig-nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nackfrom the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediatelyfollowing a start condition. the slave address byte (figure 5) contains the slave address in the most signif- icant 7 bits and the r/ w bit in the least significant bit. the ds1881 s slave address is 0101 a2 a1 a0 (binary), where a2, a1, and a0 are the values of the addresspins. the address pins allow the device to respond to one of eight possible slave addresses. by writing the correct slave address with r/ w = 0, the master indi- cates it will write data to the slave. if r/ w = 1, the mas- ter will read data from the slave. if an incorrect slaveaddress is written, the ds1881 will assume the master is communicating with another i 2 c device and ignore the communications until the next start condition is sent. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave addressbyte (r/ w = 0), write the byte of data, and generate a stop condition. the master must read the slave s acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condi-tion, writes the slave address byte (r/ w = 0), writes the desired number of data bytes and generates a stopcondition. the ds1881 is capable of writing both poten- tiometer wiper settings and the configuration register with a single write transaction. acknowledge polling: any time an eeprom location is written, the ds1881 requires the eeprom write time(t w ) after the stop condition to write the contents of the byte of data to eeprom. during the eeprom writetime, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds1881, which allows the next page to be written as soon as the ds1881 is ready to receive the data. the alternative to acknowledge polling is to wait for a maxi- mum period of t w to elapse before attempting to write again to the device.eeprom write cycles: when eeprom writes occur to the memory, the ds1881 will write to all three eeprom memory locations, even if only a single byte was modi- fied. because all three bytes are written, the bytes that were not modified during the write transaction are still subject to a write cycle. this can result in all three bytes being worn out over time by writing a single byte repeat- edly. the ds1881 s eeprom write cycles are specified in the nv memory characteristics table. the specification shown is at the worst-case temperature. if zero-crossingdetection is enabled, eeprom write cycles cannot begin until after the zero-crossing detection is complete. reading a single byte from a slave: to read a single byte from the slave, the master generates a start con- dition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of thetransfer, and generates a stop condition. when a single byte is read, it will always be the potentiometer 0 value. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a singletransfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the mas- ter reads the last byte, it nacks to indicate the end of the transfer and generates a stop condition. the first byte read will be the potentiometer 0 wiper setting. the next byte will be the potentiometer 1 wiper setting. the third byte is the configuration register byte. if an ack is issued by the master following the configuration register byte, then the ds1881 will send the potentiometer 0 wiper setting again. this round robin reading will occur as long as each byte read is followed by an ack from the master. 0 msb 7-bit slave address determines read or write function a2, a1, and a0 pin values lsb 101 a2 a1 a0 r/w figure 5. ds1881 s slave address byte downloaded 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ds1881 dual nv audio taper digital potentiometer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. heaney applications information power-supply decoupling to achieve best results, it is recommended that thepower supplies are decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as pos- sible to the voltage supplies and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the ds1881 thatrequires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be uti- lized for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the ac electrical characteristics table are within specification. scl sda gnd v dd v cc h1 h0 w1 w0 l1 l0 a1a0 a2 audioout ce decoupling capacitor decoupling capacitor 4.7k 4.7k host c audio in (ac + v cc / 2) 5v (v cc ) 20k 20k v cc / 2 = 2.5v 5v (v cc ) 5v (v dd ) ds1881 typical operating circuit package information for the latest package outline information, go towww.maxim-ic.com/dallaspackinfo . chip topology transistor count: 52,353substrate connected to ground downloaded from: http:///

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